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Electrical Properties of Bottom Gate Poly-Si TFTs by NiSi2 Seed-Induced Lateral Crystallization and Its Applications

  • Sol Kyu Lee (a1), Ki Hwan Seok (a1), Zohreh Kiaee (a1), Hyung Yoon Kim (a1), Hee Jae Chae (a1), Yong Hee Lee (a1), Gil Su Jang (a1) and Seung Ki Joo (a1)...

Abstract

In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and I on /I off ratio of ∼106.

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