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Impact of CMOS TiN metal gate process on microstructure and its correlation with electrical properties

Published online by Cambridge University Press:  30 January 2019

Pushpendra Kumar
Affiliation:
STMicroelectronics, 850 rue Jean Monnet, 38926, Crolles Cedex, France Univ. Grenoble Alpes, CEA, LETI, 38000Grenoble, France, IMEP-LAHC, Minatec/INPG, BP 257, 38016Grenoble, France
Florian Domengie
Affiliation:
STMicroelectronics, 850 rue Jean Monnet, 38926, Crolles Cedex, France
Charles Leroux
Affiliation:
Univ. Grenoble Alpes, CEA, LETI, 38000Grenoble, France,
Patrice Gergaud
Affiliation:
Univ. Grenoble Alpes, CEA, LETI, 38000Grenoble, France,
G. Ghibaudo
Affiliation:
IMEP-LAHC, Minatec/INPG, BP 257, 38016Grenoble, France
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Abstract

In this paper, the effect of TiN metal gate deposition conditions on the crystal orientation and size of TiN grains has been investigated. We have focused on process conditions that reduce the grain size or provide a unique orientation, which might impact CMOS threshold voltage variability. We have shown that the grain size can be significantly modulated by the RF power and pressure, with grain size as low as 5.2 nm. Further it has been shown that for a few optimized conditions, a unique grain orientation can be obtained. Then, the impact of these process conditions on TiN gate mechanical stress and electrical properties has been investigated. Mechanical stress and sheet resistance are modulated by pressure and RF power and have been correlated to the deposition rate and TiN grain size respectively. The effect of TiN process conditions on MOS capacitor effective workfunction (WFeff) has been investigated, and the trend is opposite to the expected modulation of the intrinsic TiN metal gate workfunction with grain orientation. On the contrary, WFeff variation is well correlated to the Ti/N ratio, suggesting an effect related to dipole at the SiO2/high-k interface.

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Copyright © Materials Research Society 2019 

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