Skip to main content Accessibility help

Thermal Stress and Failure Location Analysis for Through Silicon via in 3D Integration

  • H.-Y. Tsai (a1) and C.-W. Kuo (a1)


Through silicon via (TSV) is the critical structure for three dimensional (3D) integration, which provides vertical interconnection between stacking dies. In TSV structure, large coefficient differences of thermal expansion exist between silicon substrate, dielectric material, and filled metal. Due to the large thermal mismatch, the high thermal stress occurring at the interface of different materials would result in delamination. Therefore, thermal-mechanical reliability is a key issue for 3D integration. In this study, we investigated the thermal-mechanical stress distribution of TSV under the condition of the accelerated thermal cycling loading by finite element analysis based on a 3D model of TSV structure. Due to the thermal expansion, that the TSV structure squeezed the surface area between TSVs at a high temperature resulted in compressive stresses at the surface area between TSVs. Therefore, a proper distance between the stress-sensitive device and the TSV should be kept. The stress analysis shows that the maximum thermal stress occurs in the outside region of TSV interface and in the annular region of TSV at a high temperature and at a low temperature, respectively. This study helps to obtain a clear thermal stress distribution of TSV and possible failure regions can be determined.


Corresponding author

* Corresponding author (


Hide All
1.Beyne, E., “The rise of the 3rd dimension for system integration,” International Interconnect Technology Conference U.S.A. (2006).
2.McCracken, M. J., Koda, Y., Kim, H. J., Mayer, M., Persic, J., Hwang, J. S. and Moon, J.-T., “Explaining Nondestructive Bond Stress Data From High-Temperature Testing of Au-Al Wire Bonds,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, 3, pp. 20292036 (2013).
3.Sayyad, A. S. and Ghugal, Y. M., “Effect of Stress Concentration on Laminated Plates,” Journal of Mechanics, 29, pp. 241252 (2013).
4.Selvanayagam, C. S., Lau, J. H., Zhang, Xiaowu, Seah, S. K. W., Vaidyanathan, K. and Chai, T. C., “Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps,” IEEE Transactions on Advanced Packaging., 32, pp. 720728 (2009).
5.Ryu, S. K., Jiang, T. F., Im, J., Ho, P. S. and Huang, R., “Thermomechanical Failure Analysis of Through-Silicon Via Interface Using a Shear-Lag Model with Cohesive Zone,” IEEE Transactions on Device and Materials Reliability., 14, pp. 318326 (2014).
6.Koseski, R. P., Osborn, W. A., Stranick, S. J., DelRio, F. W., Vaudin, M. D., Dao, T., Adams, V. H. and Cook, R. F., “Micro-Scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-Filled Through-Silicon Via,” Journal of Applied Physics., 110, pp. 073517–073517-10 (2011).
7.Zhang, C. and Li, L., “Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional Ics Based on Thermomechanical Modeling,” IEEE Transactions on Electron Devices, 58, pp. 279287 (2011).
8.Ranganathan, N., Prasad, K., Balasubramanian, N. and Pey, K. L., “A Study of Thermo-Mechanical Stress and its Impact on Through-Silicon Vias,” IEEE Transactions on Electron Devices, 18, pp. 113 (2008).
9.Chen, Z. H., Song, X. H. and Liu, S., “Thermo-Mechanical Characterization of Copper Filled and Polymer Filled TSVs Considering Nonlinear Material Behaviors,” IEEE Transactions on Electron Devices, U.S.A. (2009).
10.Liu, X., Chen, Q., Dixit, P., Chatterjee, R., Tummala, R. R. and Sitaraman, S. K., “Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV),” Electronic Components and Technology Conference, U.S.A. (2009).
11.Lu, K. H., Ryu, S.-K., Zhao, Q., Zhang, X., Im, J., Huang, R. and Ho, P. S., “Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects,” Proc. 60th ECTC, Las Vegas, NV, U.S.A. (2010).
12.Athikulwongse, K., Chakraborty, A., Yang, J.-S., Pan, D. Z. and Lim, S. K., “Stress-Driven 3D-IC Placement with TSV Keep-Out Zone and Regularity Study,” IEEE/ACM ICCAD, U.S.A. (2010).
13.Ladani, L. J., “Numerical Analysis of Thermo-Mechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-Dimensional Integrated Circuits,” Microelectronic Engineering, 87, pp. 208215 (2010).
14.Che, F. X., Lim, S. P. S., Chai, T. C. and Zhang, X., “Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package with Through-Silicon Via,” IEEE Transactions on Device and Materials Reliability, 12, pp. 201208 (2012).
15.Dudek, R., Bramer, B., Irsigler, R., Rzepke, S. and Michel, B., “Thermo-Mechanical Reliability Assessment for 3D Through-Si Stacking,” 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Netherlands (2009).
16.MatWeb, Material Property Data, (1996–2013).


Thermal Stress and Failure Location Analysis for Through Silicon via in 3D Integration

  • H.-Y. Tsai (a1) and C.-W. Kuo (a1)


Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed