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Thin film backside gettering in n-type (100) Czochralski silicon during simulated CMOS process cycles

Published online by Cambridge University Press:  31 January 2011

J. Partanen
Affiliation:
Laboratory of Physics, Helsinki University of Technology, 02150 Espoo, Finland
T. Tuomi
Affiliation:
Laboratory of Physics, Helsinki University of Technology, 02150 Espoo, Finland
M. Tilli
Affiliation:
Laboratory of Physical Metallurgy, Helsinki University of Technology, 02150 Espoo, Finland
S. Hahn
Affiliation:
Siltec Silicon, 190 Independence Drive, Menlo Park, California 94025
C-C. D. Wong
Affiliation:
Integrated Device Technology, Inc., 3236 Independence Drive, Santa Clara, California 95051
F. A. Ponce
Affiliation:
Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, California 94303
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Abstract

The gettering effectiveness of various backside gettered polysilicon, silicon nitride, or poly + nitride film structures on n-type (100) Czochralski silicon wafers from a single ingot during simulated complementary-metal-oxide-semiconductor process cycles has been investigated by synchrotron section topography, breakdown voltage of 25-nm gate oxide, and minority carrier lifetime measurements. Interfacial structure was studied by cross-section transmission electron microscopy. Our studies show that for successful implementation of thin film backside gettering, good control of interactions between intrinsic gettering and thin film backside gettering during device processing cycles is critical. Thin film deposition generally increases oxygen precipitation. No extended defects propagate toward the bulk silicon. The structural and electrical quality of a denuded zone is found important. The best device yield (90%) is observed from the middle section wafers (with a 2 μm thick polysilicon backsurface coverage) which develop no recognizable bulk precipitates and stacking faults after the complete thermal cycles.

Type
Articles
Copyright
Copyright © Materials Research Society 1989

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