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Subspace Trajectory Piecewise-Linear Model Order Reduction for Nonlinear Circuits

Published online by Cambridge University Press:  03 June 2015

Xiaoda Pan*
Affiliation:
State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P.R. China
Hengliang Zhu*
Affiliation:
State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P.R. China
Fan Yang*
Affiliation:
State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P.R. China
Xuan Zeng*
Affiliation:
State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P.R. China
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Abstract

Despite the efficiency of trajectory piecewise-linear (TPWL) model order reduction (MOR) for nonlinear circuits, it needs large amount of expansion points for large-scale nonlinear circuits. This will inevitably increase the model size as well as the simulation time of the resulting reduced macromodels. In this paper, subspace TPWL-MOR approach is developed for the model order reduction of nonlinear circuits. By breaking the high-dimensional state space into several subspaces with much lower dimensions, the subspace TPWL-MOR has very promising advantages of reducing the number of expansion points as well as increasing the effective region of the reduced-order model in the state space. As a result, the model size and the accuracy of the TWPL model can be greatly improved. The numerical results have shown dramatic reduction in the model size as well as the improvement in accuracy by using the subspace TPWL-MOR compared with the conventional TPWL-MOR approach.

Type
Research Article
Copyright
Copyright © Global Science Press Limited 2013

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