Design of the VPPCs that provides the required configurability for voltage programming is hindered by several issues: complexity (a lower yield and aperture ratio), extra controlling signals (more complex external drivers), and extra operating cycles (overhead in power consumption). Moreover, the limited time provided for VT generation by the conventional addressing scheme, results in imperfect compensation. This appendix reviews different methods in increasing the VT-generation time [70, 71].

Interleaved addressing scheme

The interleaved addressing scheme depicted in Figure A.1 is based on VT generation for several rows simultaneously. The rows in a panel are divided into a few segments and the VT-generation cycle is carried out for each segment. As a result, the time assigned to the VT-generation cycle is extended by the number of rows in a segment leading to more precise compensation. Particularly, since the leakage current of a-Si:H TFTs is small (of the order of 10−14), the generated VT can be stored in a capacitor and be used for several other frames (see Figure A.1). As a result, the operating cycles during the following post-compensation frames are reduced to the programming and driving cycles similar to the operation of conventional 2-TFT pixel circuit [6]. Consequently, the power consumption associated with the external driver and with charging/discharging the parasitic capacitances is divided between the same few frames. In Figure A.1, the number of frames per segment is denoted as “h” and the number of frames per compensation interval as “l”. As seen, the driving cycle of each row starts with a delay of τP from the previous row, which is the timing budget of the programming cycle. Since τP (of the order of 10 µs) is much smaller than the frame time (of the order 16 ms), the latency effect is negligible. However, to improve the brightness accuracy, one can either change the programming direction each time, so that the average brightness lost due to latency becomes equal for all the rows, or take into consideration this effect in the programming voltage of the frames before and after the compensation cycles.