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Simulation in the Design of Digital Electronic Systems
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  • Cited by 7
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    This book has been cited by the following publications. This list is generated based on data provided by CrossRef.

    Wang, L. Olbrich, M. Barke, E. Buchner, T. and Buhler, M. 2009. Fast dynamic power estimation considering glitch filtering. p. 361.

    Ishio, S. and Ohshima, Y. 2004. Possibility of SI board fault diagnosis using adaptive image estoration to the thermograhy. Vol. D, Issue. , p. 399.

    O'Donnell, J. 2002. Overview of hydra: a concurrent language for synchronous digital circuit design. p. 9 pp.

    Hering, K. Runger, G. and Trautmann, S. 2001. Modular construction of model partitioning processes for parallel logic simulation. p. 99.

    Anwar Sadat 2001. A Compiler Driven Simulation Technique for the Analysis of Digital Logic Circuit. Journal of Applied Sciences, p. 1466.

    Burns, C. 1996. An architecture for a verilog hardware accelerator. p. 2.

    Brown, A.D. Nichols, K.G. and Zwolinski, M. 1996. Issues in the design of a logic simulator: element modelling for efficiency. IEE Proceedings - Circuits, Devices and Systems, Vol. 143, Issue. 1, p. 21.

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    Simulation in the Design of Digital Electronic Systems
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Book description

This book describes the structure of simulators suitable for use in the design of digital electronic systems. It includes the compiled code and event driven algorithms for digital electronic system simulators, together with timing verification. Limitations of the structures are also discussed. An introduction to the problems of designing models is included, partly to point to how user models might be constructed for application specific integrated circuits (ASICs) and so on, and partly to expose the limitations of the modelling process. As a guide to the use of simulators the book includes chapters which introduce the subjects of testing and design for testability. A major chapter is devoted to fault simulation. The text has an introduction to hardware accelerators and modellers.


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