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Practical Design Verification
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  • Cited by 9
  • Cited by
    This book has been cited by the following publications. This list is generated based on data provided by CrossRef.

    Abbassi, Imran Hafeez Khalid, Faiq Hasan, Osman Kamboh, Awais Mehmood and Shafique, Muhammad 2018. McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits. IEEE Access, Vol. 6, Issue. , p. 32240.

    Yu, Cunxi and Ciesielski, Maciej 2016. Formal Verification Using Don't-Care and Vanishing Polynomials. p. 284.

    Yu, Cunxi Brown, Walter and Ciesielski, Maciej 2015. Verification of arithmetic datapath designs using word-level approach — A case study. p. 1862.

    Ciesielski, Maciej Brown, Walter Liu, Duo and Rossi, Andre 2014. Function Extraction from Arithmetic Bit-Level Circuits. p. 356.

    Piccolboni, Luca and Pravadelli, Graziano 2014. Simplified stimuli generation for scenario and assertion based verification. p. 1.

    Lee, Patricia S. and Harris, Ian G. 2012. Test generation for subtractive specification errors. p. 258.

    Sanchez, Ernesto Squillero, Giovanni and Tonda, Alberto 2011. Applications of Evolutionary Computation. Vol. 6625, Issue. , p. 162.

    2010. From Control Systems to Control Software. IEEE Control Systems, Vol. 30, Issue. 6, p. 50.

    Ravotto, D. Sanchez, E. and Reorda, M. Sonza 2010. A hardware accelerated framework for the generation of design validation programs for SMT processors. p. 289.

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Book description

Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).

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