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  • Cited by 2
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    This chapter has been cited by the following publications. This list is generated based on data provided by CrossRef.

    Verma, Aishwarya Jain, Karan Mehra, Anu and Gaur, Nidhi 2016. Design and implementation of 64 bit VLIW microprocessor on 20nm and 28nm technologies. p. 213.

    Jain, Karan Verma, Aishwarya Tyagi, Devyani Mehra, Anu and Gaur, Nidhi 2017. Proposed high speed 64-bit VLIW microprocessor with modified adders. p. 316.

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  • Print publication year: 2012
  • Online publication date: November 2012

3 - Processor microarchitecture

Summary

CHAPTER OVERVIEW

The processor and its instruction set are the fundamental components of any architecture because they drive its functionality. In some sense the processor is the “brain” of a computer system, and therefore understanding how processors work is essential to understanding the workings of a multiprocessor.

This chapter first covers instruction sets, including exceptions. Exceptions, which can be seen as a software extension to the processor instruction set, are an integral component of the instruction set architecture definition and must be adhered to. They impose constraints on processor architecture. Without the need to support exceptions, processors and multiprocessors could be much more efficient but would forgo the flexibility and convenience provided by software extensions to the instruction set in various contexts. A basic instruction set is used throughout the book. This instruction set is broadly inspired by the MIPS instruction set, a rather simple instruction set. We adopt the MIPS instruction set because the fundamental concepts of processor organizations are easier to explain and grasp with simple instruction sets. However, we also explain extensions required for more complex instruction sets, such as the Intel x86, as need arises.

Since this book is about parallel architectures, we do not expose architectures that execute instructions one at a time. Thus the starting point is the 5-stage pipeline, which concurrently processes up to five instructions in every clock cycle. The 5-stage pipeline is a static pipeline in the sense that the order of instruction execution (or the schedule of instruction execution) is dictated by the compiler, an order commonly referred to as the program, thread, or process order, and the hardware makes no attempt to re-order the execution of instructions dynamically.

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Parallel Computer Organization and Design
  • Online ISBN: 9781139051224
  • Book DOI: https://doi.org/10.1017/CBO9781139051224
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