Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

Farzan Jazaeri; Jean-Michel Sallese

doi:10.1017/9781316676899

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Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

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Farzan Jazaeri, École Polytechnique Fédérale de Lausanne, Jean-Michel Sallese, École Polytechnique Fédérale de Lausanne

Publisher:: Cambridge University Press
Online publication date:: February 2018
Print publication year:: 2018
Online ISBN:: 9781316676899
DOI:: https://doi.org/10.1017/9781316676899

Subjects:: Physics and Astronomy, Condensed Matter Physics, Nanoscience and Mesoscopic Physics, Engineering, Electronic, Optoelectronic Devices, and Nanotechnology

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The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

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Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

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Frontmatter
pp i-iv

Contents
pp v-x

Foreword
pp xi-xii

Preface
pp xiii-xiv

List of Abbreviations
pp xv-xvi

List of Symbols
pp xvii-xx

1 - Introduction
pp 1-14

2 - Review on Modeling Junctionless FETs
pp 15-28

3 - The EPFL Charge-based Model of Junctionless Field-Effect Transistors
pp 29-59

4 - Model-Driven Design-Space of Junctionless FETs
pp 60-75

5 - Generalization of the Charge-based Model: Accounting for Inversion Layers
pp 76-85

6 - Predicted Performances of Junctionless FETs
pp 86-91

7 - Short-Channel Effects in Symmetric Junctionless Double-Gate FETs
pp 92-107

8 - Modeling AC Operation in Symmetric Double-Gate and Nanowire JL FETs
pp 108-138

9 - Modeling Asymmetric Operation of Double-Gate Junctionless FETs
pp 139-154

10 - Modeling Noise Behavior in Junctionless FETs
pp 155-163

11 - Carrier Mobility Extraction Methodology in JL and Inversion-Mode FETs
pp 164-173

12 - Revisiting the Junction FET: A Junctionless FET with an ∞ Gate Capacitance
pp 174-182

13 - Modeling Junctionless FET with Interface Traps Targeting Biosensor Applications
pp 183-196

Appendix A - Design-Space of Twin-Gate Junctionless Vertical Slit FETs
pp 197-199

Appendix B - Transient Off-Current in Junctionless FETs
pp 200-202

Appendix C - Derivatives of Mobile Charge Density with Respect to V GS and V DS
pp 203-203

Appendix D - Global Charge Density at Drain in Depletion Mode
pp 204-205

Appendix E - Global Charge Density at Drain in Accumulation Mode
pp 206-207

Appendix F - The EPFL Junctionless MODEL
pp 208-214

References
pp 215-230

Index
pp 231-233

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Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

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