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  • Print publication year: 2016
  • Online publication date: April 2016

6 - Stacked-transistor mm-wave power amplifiers



A dominant theme in the evolution of integrated electronics over past decades has been Moore's law, which has led to development of silicon-based transistors with dramatically improved operating speeds and levels of integration, as well as reduced power dissipation. Although the driving motivation for the technology development has been primarily application to digital circuits, silicon-based transistors are poised, by virtue of their very high frequency response, to provide mm-wave and THz circuits with also dramatically improved performance as well as low cost. One of the tradeoffs that has been necessary in the development of scaled silicon devices, however, has been a reduction in voltage handling capability. As a result, conventional scaled silicon transistors are not very well suited to power amplifiers, which perform best with high voltage swings along with high current swings. Recent research, however, has pointed to a circuit design approach that can overcome to a considerable degree the limitations of the basic transistors: the technique of series-connection, or stackingİ of multiple devices to generate a composite structure that can handle higher voltages. The stacking technique has opened the door to higher output power as well as higher efficiency and greater bandwidth, since the resulting impedance transformations needed to generate amplifier outputs at 50 ohm levels become easier to implement with low loss and high bandwidth. This chapter describes in detail the background, design considerations and benefits of stacked Si devices in mm-wave power amplifiers. Emphasis is given to stacked CMOS devices, although bipolar transistors and HBTs can also be stacked as described in Chapter 5. A review of Si FET characteristics is first given, along with a description of the impact of voltage handling on power amplifier characteristics. Stacked FET amplifiers at low microwave frequencies, which are emerging as important contenders for cell phone handsets, is then reviewed. Key design considerations for stacking at mm-wave frequencies are then presented. The chapter also describes a number of mm-wave power amplifier example designs in detail.

Motivation for stacking

As a result of Moore's law, transistor current gain cut-off frequencies (fT) have been increasing rapidly as the transistor dimensions have been reduced. Figure 6.1 illustrates recent fT measurement results for n-MOS devices at the 90nm node and below, as a function of gate length (which typically is smaller than the metallization half-pitch which defines the technology node).

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[1] C.-H., Jan, M., Agostinelli, H., Deshpande, M., El-Tanani, W., Hafez, U., Jalan, L., Janbay, M., Kang, H., Lakdawala, J., Lin, Y.-L., Lu, S., Mudanai, J., Park, A., Rahman, J., Rizk, W.-K., Shin, K., Soumyanath, H., Tashiro, C., Tsai, P., Vandervoorn, J. Y., Yeh, and P., Bai, “RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications,” in Electron Devices Meeting (IEDM), 2010 IEEE International, Dec 2010, pp. 27.2.1–27.2.4.
[2] “2011 International Technology Roadmap for Semiconductors,”
[3] M., Apostolidou, M. van der, Heijden, D., Leenaerts, J., Sonsky, A., Heringa, and I., Volokhine, “A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off,” Solid-State Circuits, IEEE Journal of, vol. 44, no. 5, pp. 1372–1379, May 2009.
[4] A., Ezzeddine and H., Huang, “The high voltage/high power FET (HiVP),” in Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE, June 2003, pp. 215–218.
[5] H., Dabag, B., Hanafi, F., Golcuk, A., Agah, J., Buckwalter, and P., Asbeck, “Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers,” Microwave Theory and Techniques, IEEE Transactions on, vol. 61, no. 4, pp. 1543–1556, April 2013.
[6] N., Sokal and A., Sokal, “Class E – A new class of high-efficiency tuned single-ended switching power amplifiers,” Solid-State Circuits, IEEE Journal of, vol. 10, no. 3, pp. 168–176, Jun 1975.
[7] O., Ogunnika and A., Valdes-Garcia, “A 60GHz Class-E Tuned Power Amplifier with PAE >25% in 32nm SOI CMOS,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE, June 2012, pp. 65–68.
[8] A., Mazzanti, L., Larcher, R., Brama, and F., Svelto, “Analysis of reliability and power efficiency in cascode class-E PAs,” Solid-State Circuits, IEEE Journal of, vol. 41, no. 5, pp. 1222–1229, May 2006.
[9] O., Lee, J., Han, K. H., An, D. H., Lee, K.-S., Lee, S., Hong, and C.-H., Lee, “A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers,” Solid-State Circuits, IEEE Journal of, vol. 45, no. 10, pp. 2184–2197, Oct 2010.
[10] A., Chakrabarti, J., Sharma, and H., Krishnaswamy, “Dual-Output Stacked Class-EE Power Amplifiers in 45nm SOI CMOS for Q-Band Applications,” in Compound Semiconductor Integrated Circuit Symposium (CSICS), 2012 IEEE, Oct 2012, pp. 1–4.
[11] M., Shifrin, Y., Ayasli, and P., Katzin, “A new power amplifier topology with series biasing and power combining of transistors,” in Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1992. Digest of Papers, IEEE 1992, June 1992, pp. 39–41.
[12] K. J., Dean, Transistors, Theory and Circuitry. McGraw-Hill, New York, 1964.
[13] M., Rodwell, S., Jaganathan, and S. T., Allen, “Series-connected microwave power amplifiers with voltage feedback and method of operation for the same,” U.S. Patent 5 945 879.
[14] J., McRory, G., Rabjohn, and R., Johnston, “Transformer coupled stacked FET power amplifiers,” Solid-State Circuits, IEEE Journal of, vol. 34, no. 2, pp. 157–161, Feb 1999.
[15] T., Sowlati and D., Leenaerts, “A 2.4-GHz 0.18- um CMOS self-biased cascode power amplifier,” Solid-State Circuits, IEEE Journal of, vol. 38, no. 8, pp. 1318–1324, Aug 2003.
[16] S., Pornpromlikit, J., Jeong, C., Presti, A., Scuderi, and P., Asbeck, “A Watt-Level Stacked- FET Linear Power Amplifier in Silicon-on-Insulator CMOS,” Microwave Theory and Techniques, IEEE Transactions on, vol. 58, no. 1, pp. 57–64, Jan 2010.
[17] S., Leuschner, J.-E., Mueller, and H., Klar, “A 1.8GHz wide-band stacked-cascode CMOS power amplifier for WCDMA applications in 65nm standard CMOS,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, June 2011, pp. 1–4.
[18] A., Ezzeddine, H.-C., Huang, and J., Singer, “UHiFET - A new high-frequency High-Voltage device,” in Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International, June 2011, pp. 1–4.
[19] A., Agah, J., Jayamon, P., Asbeck, L., Larson, and J., Buckwalter, “Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS,” Solid-State Circuits, IEEE Journal of, vol. 49, no. 5, pp. 1148–1157, May 2014.
[20] A., Balteanu, I., Zarkas, E., Dacquay, A., Tomkins, and S., Voinigescu, “A 45-GHz, 2-bit Power DAC with 24.3 dBm Output Power, >14 Vpp Differential Swing, and 22% Peak PAE in 45- nm SOI CMOS,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE, June 2012, pp. 319–322.
[21] A., Chakrabarti and H., Krishnaswamy, “High power, high efficiency stacked mm-Wave Class-E-like power amplifiers in 45nm SOI CMOS,” in Custom Integrated Circuits Conference (CICC), 2012 IEEE, Sept. 2012, pp. 1–4.
[22] A., Chakrabarti and H., Krishnaswamy, “An Improved Analysis and Design Methodology for RF Class-E Power Amplifiers with Finite DC-feed Inductance and Switch On-Resistance,” in Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, May 2012, pp. 1763–1766.
[23] S., Kee, “The Class E/F Family of Harmonic-Tuned Switching Power Amplifiers,” Ph.D. dissertation, California Institute of Technology, Pasadena, California, 2001. [Online]. Available: :etd-04262005-152703
[24] A., Chakrabarti and H., Krishnaswamy, “High-Power, High-Efficiency, Class-E-like, Stacked mm-wave PAs in SOI and bulk CMOS: Theory and Implementation,” IEEE Transactions on Microwave Theory and Techniques, (accepted) to appear.
[25] J. wei, Lai and A., Valdes-Garcia, “A 1V 17.9dBm 60GHz Power Amplifier In Standard 65nm CMOS,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, Feb 2010, pp. 424–425.
[26] R., Bhat, A., Chakrabarti, and H., Krishnaswamy, “Large-scale power-combining and linearization in watt-class mm-wave CMOS power amplifiers,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2013 IEEE, June 2013, pp. 283–286.
[27] J., Jayamon, A., Agah, B., Hanafi, H., Dabag, J., Buckwalter, and P., Asbeck, “A W-band stacked FET power amplifier with 17 dBm Psat in 45-nm SOI MOS,” in Radio and Wireless Symposium (RWS), 2013 IEEE, Jan 2013, pp. 256–258.