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  • Print publication year: 2015
  • Online publication date: August 2015

7 - Analog-assisted digital design in mobile SoCs


Transistor technology scaling has deviated from the ideal constant-field scaling discussed by Dennard et al. in [1]. In particular, since the 90-nm technology node, the supply voltage has been going down slowly, if at all. This non-ideal scaling has made digital design more difficult for mobile SoCs. As a result, a number of mixed-signal techniques have been introduced to mitigate the reduced power benefits of scaling.

This chapter first gives an overview of the main digital design challenges for mobile SoCs in nanometer CMOS technologies. Then, it discusses several mixed-signal assist techniques to help with voltage scaling, voltage regulation, voltage droop management, inrush current management, thermal management, and silicon aging.

Digital design challenges for mobile SoCs

SoCs targeting mobile applications face a number of digital design challenges in nanometer CMOS technologies. These challenges are related to maximizing energy efficiency, controlling process variability, limiting power-supply noise, managing temperature, and silicon aging. They are certainly not unique to mobile SoCs, but are particularly important for such applications.

Energy efficiency

Mobile SoCs need to be low-power and energy-efficient. However, the power dissipation per device is no longer scaling well [2]. This puts more pressure on the development of new design techniques to reduce the dynamic and leakage power consumption of SoCs.

It is useful to remind ourselves that the dynamic power Pdyn for a net switching α times per clock cycle is given by:

Pdyn=α CV2f,

where C is the switched capacitance, V is the supply voltage, and f is the clock frequency. Some of the most common ways to reduce the dynamic power include using clock gating to lower the switching activity of sequential elements, wire length or gate sizing optimizations to reduce the switched capacitance, supply voltage scaling, and frequency scaling. Reducing the voltage has a quadratic effect on the dynamic power and is especially effective. This has led to the proliferation of the number of voltage and frequency domains for the various components (cores) used in an SoC. Scaling the voltage requires a regulator that can be programmed to produce multiple voltage levels. Buck regulators and low dropout regulators are typically used for this. Frequency scaling is usually done using a programmable clock generator such as a phase-locked loop (PLL) or frequency-locked loop (FLL), or a frequency divider.

Energy efficiency also requires the adoption of leakage control techniques.

[1] Dennard, R. H., Gaensslen, F. H., Yu, H.-N., Rideout, V. L., Bassous, E., and LeBlanc, A. R., “Design of ion-implanted MOSFET's with very small physical dimensions,” IEEE Journal of Solid-State Circuits, vol. 9, no. 5, Oct. 1974.
[2] Horowitz, M., Alon, E., Patil, D., Naffziger, S., Kumar, R., and Bernstein, K., “Scaling, power, and the future of CMOS,” IEEE International Electron Device Meeting, 2005.
[3] Pang, L. T., Qian, K., Spanos, C. J., and Nikolić, B., “Measurement and analysis of variability in 45 nm strained-Si CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 44, no. 8, Aug. 2009.
[4] Kuhn, K. J., Giles, M. D., Becher, D., et al., “Process technology variation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, Aug. 2011.
[5] Saha, S. K., “Modeling process variability in scaled CMOS technology,” IEEE Design and Test of Computers, vol. 27, no. 2, Mar.-Apr. 2010.
[6] Saint-Laurent, M. and Swaminathan, M., “Impact of power-supply noise on timing in high-frequency microprocessors,” IEEE Transactions on Advanced Packaging, vol. 27, no. 1, Feb. 2004.
[7] Kumar, R. and Kursun, V., “Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits,” IEEE Transactions on Circuits and Systems–II, vol. 53, no. 10, Oct. 2006.
[8] Pobegen, G. and Grasser, T., “On the distribution of NBTI time constants on a long, temperature-accelerated time scale,” IEEE Transactions on Electron Devices, vol. 60, no. 7, July 2013.
[9] Joshi, K., Mukhopadhyay, S., Goel, N., and Mahapatra, S., “A consistent physical framework for N and P BTI in HKMG MOSFETs,” IEEE International Reliability Physics Symposium, 2012.
[10] Drake, A., Senger, R., Deogun, H., et al., “A distributed critical-path timing monitor for a 65nm high-performance microprocessor,” IEEE Solid-State Circuits Conference, 2007.
[11] Floyd, M. S., Drake, A., Schwartz, N. S., et al., “Runtime power reduction capability of the IBM POWER7+ chip,” IBM Journal of Research and Development, vol. 57, no. 6, 2013.
[12] Das, S., Roberts, D., Lee, S., et al., “A self-tuning DVS processor using delay-error detection and correction,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, Apr. 2006.
[13] Das, S., Tokunaga, C., Pant, S., et al., “Razor II: in situ error detection and correction for PVT and SER tolerance,” IEEE Journal of Solid-State Circuits, vol. 44, no. 1, Jan. 2009.
[14] Schrom, G., Hazucha, P., Paillet, F.. et al., “A 100MHz eight-phase buck converter delivering 12A in 25mm2 using air-core inductors,” IEEE Applied Power Electronics Conference, 2007.
[15] Burton, E. A., Schrom, G., Paillet, F., et al., “FIVR – fully integrated voltage regulators on 4th generation Intel core SoCs,” IEEE Applied Power Electronics Conference, 2014.
[16] Kursun, V., Schrom, G., De, V. K., Friedman, E. G., and Narendra, S. G., “Cascode buffer for monolithic voltage conversion operating at high input supply voltages,” IEEE International Symposium on Circuits and Systems, 2005.
[17] Rocha, J. F.da, Santos, M. B.dos, Costa, J. M. Dores, and Lima, F. A., “Level shifters and DCVSL for a low-voltage CMOS 4.2-V buck converter,” IEEE Transactions on Industrial Electronics, vol. 55, no. 9, 2008.
[18] Torres, J., El-Nozahi, M., Amer, A., et al., “Low drop-out voltage regulators: capacitor-less architecture comparison,” IEEE Circuits and Systems Magazine, vol. 14, no. 2, 2014.
[19] Seeman, M. D. and Sanders, S. R., “Analysis and optimization of switched-capacitor DC-DC converters,” IEEE Transactions on Power Electronics, vol. 23, no. 2, 2008.
[20] Jain, R., Geuskens, B., Khellah, M., et al., “A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS,” IEEE Symposium on VLSI Circuits, 2013.
[21] Anderson, T. M., Krismer, F., Kolar, J. W., et al., “A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS,” IEEE International Symposium on Solid-State Circuits, 2014.
[22] Pant, S. and Blaauw, D., “A charge-injection-based active-decoupling technique for inductive-supply-noise suppression,” IEEE International Solid-State Circuits Conference, 2008.
[23] Restle, P. J., Franch, R. L., James, N. K., et al., “Timing uncertainty measurements on the Power5 microprocessor,” IEEE International Conference on Solid-State Circuits, 2004.
[24] Ang, M., Salem, R., Taylor, A., “An on-chip voltage regulator using switched decoupling capacitors,” IEEE International Solid-State Circuits Conference, 2000.
[25] Meng, X. and Saleh, R., “An improved active decoupling capacitor for hot-spot supply noise reduction in ASIC designs,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, Feb. 2009.
[26] Gu, J., Eom, H., and Kim, C. H., “On-chip supply noise regulation using a low-power digital switched decoupling capacitor circuit,” IEEE Journal of Solid-State Circuits, vol. 44, no. 6, June 2009.
[27] Tsukada, T., Hashimoto, Y., Sakata, K., Okada, H., and Ishibashi, K., “An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, Jan. 2005.
[28] Gu, J., Harjani, R., and Kim, C. H., “Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ICs,” IEEE Transactions on VLSI Systems, vol. 17, no. 2, Feb. 2009.
[29] Fisher, T., Desai, J., Doyle, B., Naffziger, S., and Patella, B., “A 90-nm variable frequency clock system for a power-managed titanium architecture processor,” IEEE Journal of Solid-State Circuits, vol. 41, no. 1, Jan. 2006.
[30] Grenat, A., Pant, S., Rachala, R., and Naffziger, S., “Adaptive clocking system for improved power efficiency in a 28nm x86–64 microprocessor,” IEEE International Solid-State Circuits Conference, 2014.
[31] Hsieh, P.-H., Maxey, J., and Yang, C.-H. K., “A phase-selecting digital phase-locked loop with bandwidth tracking in 65-nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, Apr. 2010.
[32] Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J., “1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, Aug 1995.
[33] Shigematsu, S., Mutoh, S., Matsuya, Y., Tanabe, Y., and Yamada, J., “A 1-V high-speed MTCMOS circuit scheme for power-down application circuits,” IEEE Journal of Solid-State Circuits, vol. 32, no. 6, June 1997.
[34] Saint-Laurent, M., Bassett, P., Lin, K., et al., “A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications,” IEEE Journal of Solid-State Circuits, vol. 50, no. 1, Jan. 2015.
[35] Pertijs, M. A. P., Makinwa, K. A. A., and Huijsing, J. H., “A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1 °C from –55 °C to 125 °C,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, Dec. 2005.
[36] Lakdawala, H., Li, Y. W., Raychowdhury, A., Taylor, G., and Soumyanath, K., “A 1.05 V 1.6 mW, 0.45 °C 3σ resolution ΣΔ based temperature sensor with parasitic resistance compensation in 32 nm digital CMOS process,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, Dec. 2009.
[37] Keane, J., Wang, X., Persaud, D., and Kim, C. H., “An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, Apr. 2010.