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  • Print publication year: 2015
  • Online publication date: August 2015

7 - Analog-assisted digital design in mobile SoCs

Summary

Transistor technology scaling has deviated from the ideal constant-field scaling discussed by Dennard et al. in [1]. In particular, since the 90-nm technology node, the supply voltage has been going down slowly, if at all. This non-ideal scaling has made digital design more difficult for mobile SoCs. As a result, a number of mixed-signal techniques have been introduced to mitigate the reduced power benefits of scaling.

This chapter first gives an overview of the main digital design challenges for mobile SoCs in nanometer CMOS technologies. Then, it discusses several mixed-signal assist techniques to help with voltage scaling, voltage regulation, voltage droop management, inrush current management, thermal management, and silicon aging.

Digital design challenges for mobile SoCs

SoCs targeting mobile applications face a number of digital design challenges in nanometer CMOS technologies. These challenges are related to maximizing energy efficiency, controlling process variability, limiting power-supply noise, managing temperature, and silicon aging. They are certainly not unique to mobile SoCs, but are particularly important for such applications.

Energy efficiency

Mobile SoCs need to be low-power and energy-efficient. However, the power dissipation per device is no longer scaling well [2]. This puts more pressure on the development of new design techniques to reduce the dynamic and leakage power consumption of SoCs.

It is useful to remind ourselves that the dynamic power Pdyn for a net switching α times per clock cycle is given by:

Pdyn=α CV2f,

where C is the switched capacitance, V is the supply voltage, and f is the clock frequency. Some of the most common ways to reduce the dynamic power include using clock gating to lower the switching activity of sequential elements, wire length or gate sizing optimizations to reduce the switched capacitance, supply voltage scaling, and frequency scaling. Reducing the voltage has a quadratic effect on the dynamic power and is especially effective. This has led to the proliferation of the number of voltage and frequency domains for the various components (cores) used in an SoC. Scaling the voltage requires a regulator that can be programmed to produce multiple voltage levels. Buck regulators and low dropout regulators are typically used for this. Frequency scaling is usually done using a programmable clock generator such as a phase-locked loop (PLL) or frequency-locked loop (FLL), or a frequency divider.

Energy efficiency also requires the adoption of leakage control techniques.

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