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• Print publication year: 2015
• Online publication date: February 2019

14 - Sequential logic

from Part IV - Synchronous sequential logic

Summary

The output of sequential logic depends not only on its input, but also on its state, which may reflect the history of the input. We form a sequential logic circuit via feedback – feeding state variables computed by a block of combinational logic back to its input. General sequential logic, with asynchronous feedback, can become complex to design and analyze due to multiple state bits changing at different times. We simplify our design and analysis tasks in this chapter by restricting ourselves to synchronous sequential logic, in which the state variables are held in a register and updated on each rising edge of a clock signal (clk).

The behavior of a synchronous sequential logic circuit, or finite-state machine (FSM), is completely described by two logic functions: one that computes its next state as a function of its input and present state, and one that computes its output – also as a function of its input and present state. We describe these two functions by means of a state table, or graphically with a state diagram. If states are specified symbolically, a state assignment maps the symbolic states onto a set of bit vectors – both binary and one-hot state assignments are commonly used.

Given a state table (or state diagram) and a state assignment, the task of implementing a finite-state machine is a simple one of synthesizing the next-state and output logic functions. For a one-hot state encoding, the synthesis is particularly simple because each state maps to a separate flip-flop and all edges in the state diagram leading to a state map into a logic function on the input of that flip-flop. For binary encodings, Karnaugh maps for each bit of the state vector are written and reduced to logic equations.

Finite-state machines can be implemented in VHDL by creating a state register to hold the current state, and describing the next-state and output functions with combinational logic descriptions, such as case statements as described in Chapter 7. State assignments should be specified using constants to allow them to be changed without altering the machine description itself. Special attention should be given to resetting the FSM to a known state at startup.